(China (Mainland))
Product Summary
The A67L93361E-7.5F is a Flow-through ZeBL SRAM. It employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L93361E-7.5F integrates a 1M×18, 512K×36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. The A67L93361E-7.5F is optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. The synchronous inputs include all address, all data inputs, active low chip enable (CE), two additional chip enables for easy depth expansion (CE2, CE2), cycle start input (ADV/ LD ), synchronous clock enable ( CEN), byte write enables ( BW1 , BW2 , BW3 , BW4 ) and read/write (R/W).
Parametrics
A67L93361E-7.5F absolute maximum ratings: (1)Power Supply Voltage (VCC): -0.3V to +4.6V; (2)Voltage Relative to GND for any Pin Except VCC (Vin, Vout): -0.3V to VCC +0.3V; (3)Operating Temperature (Topr): 0℃ to 70℃; (4)Storage Temperature (Tbias): -10℃ to 85℃; (5)Storage Temperature (Tstg): -55℃ to 125℃.
Features
A67L93361E-7.5F features: (1)Fast access time: 6.5/7.5/8.5ns (153, 133, 117MHz); (2)Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization; (3)Signal +3.3V ±5% power supply; (4)Individual Byte Write control capability; (5)Clock enable ( CEN) pin to enable clock and suspend operations; (6)Clock-controlled and registered address, data and control signals; (7)Registered output for pipelined applications; (8)Three separate chip enables allow wide range of options for CE control, address pipelining; (9)Internally self-timed write cycle; (10)Selectable BURST mode (Linear or Interleaved); (11)SLEEP mode (ZZ pin) provided; (12)Available in 100 pin LQFP package.
Diagrams
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