Product Summary

The ADF4001BRUZ-R7 clock generator can be used to implement clock sources for PLLs that require very low noise, stable reference signals. The ADF4001BRUZ-R7 consists of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, and a programmable 13-bit N counter. In addition, the 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and VCO (voltage controlled oscillator) or VCXO (voltage controlled crystal oscillator). The N minimum value of 1 allows flexibility in clock generation.

Parametrics

ADF4001BRUZ-R7 absolute maximum ratings:(1)AVDD to GND: -0.3 V to +7 V; (2)AVDD to DVDD: 0 V to +0.3 V; (3)VP to GND: -0.3 V to +7 V; (4)VP to AVDD: -0.3 V to +5.5 V; (5)Digital I/O Voltage to GND: -0.3 V to VDD + 0.3 V; (6)Analog I/O Voltage to GND: -0.3 V to VP + 0.3 V; (7)REFIN, RFINA, RFINB to GND: -0.3 V to VDD + 0.3 V; (8)RFINA to RFINB: ±320 mV; (9)Operating Temperature Range: Industrial (B Version) -40°C to +85°C; (10)Storage Temperature Range: -65°C to +150°C; (11)Maximum Junction Temperature: 150°C.

Features

ADF4001BRUZ-R7 features:(1)200 MHz Bandwidth; (2)2.7 V to 5.5 V Power Supply; (3)Separate Charge Pump Supply (VP) Allows Extended Tuning Voltage in 5 V Systems; (4)Programmable Charge Pump Currents; (5)3-Wire Serial Interface; (6)Hardware and Software Power-Down Mode; (7)Analog and Digital Lock Detect; (8)Hardware Compatible to the ADF4110/ ADF4111/ ADF4112/ ADF4113; (9)Typical Operating Current 4.5 mA; (10)Ultralow Phase Noise; (11)16-Lead TSSOP; (12)20-Lead LFCSP.

Diagrams

ADF4001BRUZ-R7 pin connection

Image Part No Mfg Description Data Sheet Download Pricing
(USD)		 Quantity
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