ADF4108BCPZ

Product Summary

The ADF4108BCPZ frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. ADF4108BCPZ consists of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the ADF4108BCPZ is used with an external loop filter and voltage controlled oscillator (VCO). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost.

Parametrics

ADF4108BCPZ absolute maximum ratings: (1)AVDD to GND: –0.3 V to +3.9 V; (2)AVDD to DVDD: –0.3 V to +0.3 V; (3)VP to GND: –0.3 V to +5.8 V; (4)VP to AVDD: –0.3 V to +5.8 V; (5)Digital I/O Voltage to GND: –0.3 V to VDD + 0.3 V; (6)Analog I/O Voltage to GND: –0.3 V to VP + 0.3 V; (7)REFIN, RFINA, RFINB to GND: –0.3 V to VDD + 0.3 V; (8)Operating Temperature Range Industrial (B Version): –40℃ to +85℃; (9)Storage Temperature Range: –65℃ to +125℃; (10)Maximum Junction Temperature: 150℃; (11)TSSOP θJA Thermal Impedance: 112℃/W; (12)CSP θJA Thermal Impedance (Paddle Soldered): 30.4℃/W; (13)Reflow Soldering, Peak Temperature (60 sec): 260; Time at Peak Temperature: 40 sec; (14)Transistor Count: CMOS, 6425; Bipolar, 303.

Features

ADF4108BCPZ features: (1)8.0 GHz bandwidth; (2)3.2 V to 3.6 V power supply; (3)Separate charge pump supply (VP) allows extended tuning voltage in 3.3 V systems; (4)Programmable, dual modulus prescaler 8/9, 16/17, 32/33, or 64/65; (5)Programmable charge pump currents; (6)Programmable antibacklash pulse width; (7)3-wire serial interface; (8)Analog and digital lock detect; (9)Hardware and software power-down mode; (10)Loop filter design possible with ADIsimPLL.

Diagrams