(China (Mainland))
Product Summary
The CD4073BE is a CMOS AND gate. The CD4073BE provides the system designer with direct implementation of the AND function and supplement the existing family of CMOS gate. The CD4073BE is supplied in 14-lead hermetic dual-in-line ceramic package (F3A suffix), 14-lead dual-in-line plastic package (E suffix), 14-lead small-outline package (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline package (PW and PWR suffixes).
Parametrics
CD4073BE absolute maximum ratings: (1)DC supply-voltage range, (VDD)voltages referenced to Vss terminal: -0.5V to +20V; (2)input voltage range, all inputs: -0.5 to VDD +0.5V; (3)DC input current, any one input: ±10mA; (4)power dissipation per package(PD), for TA =-55℃ to +100℃: 500mW; (5) power dissipation per package(PD),for TA =+100℃ to +125℃: 12mW to 200mW; (6)device dissipation per output transistor, for TA =full package-temperature range(all package types): 100Mw; (7)operating-temperature range(TA): -55℃ to +125℃; (8)storage temperature range(Tstg): -65℃ to +150℃; (8)lead temperature(during soldering, at distance 1/16±1/32 inch from case for 10s max): +265℃.
Features
CD4073BE features: (1)Medium-Speed Operation-tPLH, tPHL =60ns(typ.) at VDD=10V; (2)100% tested for quiescent current at 20V; (3)Maximum input current of 1μA at 18V over full package-temperature range: 100nA at 18V and 25℃; (4)Noise margin (full package-temperature range):1V at VDD=5V,2V at VDD=10V,2.5V at VDD=15V; (5)Standardized, symmetrical output characteristics; (6)5-V,10-V,and 15-V parametric ratings; (7)Meets all requirements of JEDEC Tentative Standard No.13B,”Standard Specifications for Description of ’B’ Series CMOS Devices”.
Diagrams
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 CD4073BE |
Texas Instruments |
Gates (AND / NAND / OR / NOR) Triple 3-Input |
Data Sheet |
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CD4073BEE4 |
Texas Instruments |
Gates (AND / NAND / OR / NOR) Triple 3-Input |
Data Sheet |
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